// MMX optimization, coded by Shih-Wea Liao #define BITS_INV_ACC 4 // 4 or 5 for IEEE // 5 yields higher accuracy, but lessens dynamic range on the input matrix #define SHIFT_INV_ROW (16 - BITS_INV_ACC) #define SHIFT_INV_COL (1 + BITS_INV_ACC + 14) #define RND_INV_ROW (1 << (SHIFT_INV_ROW-1)) #define RND_INV_COL (1 << (SHIFT_INV_COL-1)) #define RND_INV_CORR (RND_INV_COL - 1) const static long r_inv_row[2] = { RND_INV_ROW, RND_INV_ROW}; const static long r_inv_col[2] = {RND_INV_COL, RND_INV_COL}; const static long r_inv_corr[2] = {RND_INV_CORR, RND_INV_CORR}; static const short tab_i_01234567[] = { 16384, 16384, 16384, -16384, 21407, 8867, 8867, -21407, 16384, -16384, 16384, 16384, -8867, 21407, -21407, -8867, 22725, 12873, 19266, -22725, 19266, 4520, -4520, -12873, 12873, 4520, 4520, 19266, -22725, 19266, -12873, -22725, }; #define INP eax #define OUT ecx #define TABLE ebx #define round_inv_row edx #define round_inv_col edx #define ROW_STRIDE 16 static __int64 qwTemp[32]; __forceinline static void idct_mmx32_rows(short *block); __forceinline static void idct_mmx32_cols(short *block); // public interface to MMX32 IDCT 8x8 operation void __stdcall idct_int32(short *block) { idct_mmx32_rows(block); idct_mmx32_cols(block); __asm emms } static void idct_mmx32_rows(short *block) { __asm { mov INP, dword ptr [block] mov edi, 0x00 lea TABLE, dword ptr [tab_i_01234567] lea OUT, dword ptr [qwTemp] lea round_inv_row, dword ptr [r_inv_row] lpa: movq mm0, qword ptr [INP] movq mm1, qword ptr [INP+8] movq mm2, mm0 movq mm3, qword ptr [TABLE] punpcklwd mm0, mm1 movq mm5, mm0 punpckldq mm0, mm0 movq mm4, qword ptr [TABLE+8] punpckhwd mm2, mm1 pmaddwd mm3, mm0 movq mm6, mm2 movq mm1, qword ptr [TABLE+32] punpckldq mm2, mm2 pmaddwd mm4, mm2 punpckhdq mm5, mm5 pmaddwd mm0, qword ptr [TABLE+16] punpckhdq mm6, mm6 movq mm7, qword ptr [TABLE+40] pmaddwd mm1, mm5 paddd mm3, qword ptr [round_inv_row] pmaddwd mm7, mm6 pmaddwd mm2, qword ptr [TABLE+24] paddd mm3, mm4 pmaddwd mm5, qword ptr [TABLE+48] movq mm4, mm3 pmaddwd mm6, qword ptr [TABLE+56] paddd mm1, mm7 paddd mm0, qword ptr [round_inv_row] psubd mm3, mm1 psrad mm3, SHIFT_INV_ROW paddd mm1, mm4 paddd mm0, mm2 psrad mm1, SHIFT_INV_ROW paddd mm5, mm6 movq mm4, mm0 paddd mm0, mm5 psubd mm4, mm5 add INP, 16 psrad mm4, SHIFT_INV_ROW psrad mm0, SHIFT_INV_ROW packssdw mm4, mm3 packssdw mm1, mm0 movq mm7, mm4 psrld mm4, 16 movq qword ptr [OUT], mm1 pslld mm7, 16 por mm7, mm4 movq mm3, qword ptr [TABLE] movq qword ptr [OUT+8], mm7 add edi, 0x01 add OUT, 16 cmp edi, 0x08 jl lpa lea OUT, dword ptr [qwTemp] movq mm0, qword ptr [OUT+ROW_STRIDE*0] movq mm1, qword ptr [OUT+ROW_STRIDE*1] movq mm4, mm0 movq mm2, qword ptr [OUT+ROW_STRIDE*2] punpcklwd mm0, mm1 movq mm3, qword ptr [OUT+ROW_STRIDE*3] punpckhwd mm4, mm1 movq mm6, mm2 punpcklwd mm2, mm3 punpckhwd mm6, mm3 movq mm1, mm0 mov INP, dword ptr [block] punpckldq mm0, mm2 movq mm3, mm4 punpckhdq mm1, mm2 movq qword ptr [INP+ROW_STRIDE*0], mm0 punpckldq mm4, mm6 movq mm0, qword ptr [OUT+ROW_STRIDE*4+8] punpckhdq mm3, mm6 movq qword ptr [INP+ROW_STRIDE*2], mm4 movq mm4, mm0 movq qword ptr [INP+ROW_STRIDE*1], mm1 movq mm1, qword ptr [OUT+ROW_STRIDE*5+8] movq qword ptr [INP+ROW_STRIDE*3], mm3 punpcklwd mm0, mm1 movq mm2, qword ptr [OUT+ROW_STRIDE*6+8] punpckhwd mm4, mm1 movq mm3, qword ptr [OUT+ROW_STRIDE*7+8] movq mm6, mm2 punpcklwd mm2, mm3 movq mm1, mm0 punpckhwd mm6, mm3 movq mm3, mm4 punpckldq mm0, mm2 punpckhdq mm1, mm2 movq qword ptr [INP+ROW_STRIDE*4+8], mm0 punpckldq mm4, mm6 movq mm0, qword ptr [OUT+ROW_STRIDE*4] punpckhdq mm3, mm6 movq qword ptr [INP+ROW_STRIDE*6+8], mm4 movq mm4, mm0 movq qword ptr [INP+ROW_STRIDE*5+8], mm1 movq mm1, qword ptr [OUT+ROW_STRIDE*5] movq qword ptr [INP+ROW_STRIDE*7+8], mm3 punpcklwd mm0, mm1 movq mm2, qword ptr [OUT+ROW_STRIDE*6] punpckhwd mm4, mm1 movq mm3, qword ptr [OUT+ROW_STRIDE*7] movq mm6, mm2 punpcklwd mm2, mm3 movq mm1, mm0 punpckhwd mm6, mm3 movq mm3, mm4 punpckldq mm0, mm2 punpckhdq mm1, mm2 movq qword ptr [INP+ROW_STRIDE*0+8], mm0 punpckldq mm4, mm6 movq mm0, qword ptr [OUT+ROW_STRIDE*0+8] punpckhdq mm3, mm6 movq qword ptr [INP+ROW_STRIDE*2+8], mm4 movq mm4, mm0 movq qword ptr [INP+ROW_STRIDE*1+8], mm1 movq mm1, qword ptr [OUT+ROW_STRIDE*1+8] movq qword ptr [INP+ROW_STRIDE*3+8], mm3 punpcklwd mm0, mm1 movq mm2, qword ptr [OUT+ROW_STRIDE*2+8] punpckhwd mm4, mm1 movq mm3, qword ptr [OUT+ROW_STRIDE*3+8] movq mm6, mm2 punpcklwd mm2, mm3 movq mm1, mm0 punpckhwd mm6, mm3 movq mm3, mm4 punpckldq mm0, mm2 punpckhdq mm1, mm2 movq qword ptr [INP+ROW_STRIDE*4], mm0 punpckldq mm4, mm6 movq qword ptr [INP+ROW_STRIDE*5], mm1 punpckhdq mm3, mm6 movq qword ptr [INP+ROW_STRIDE*6], mm4 movq qword ptr [INP+ROW_STRIDE*7], mm3 } } static void idct_mmx32_cols(short *block) { __asm { mov INP, dword ptr [block] mov edi, 0x00 lea TABLE, dword ptr [tab_i_01234567] lea OUT, dword ptr [qwTemp] lea round_inv_col, dword ptr [r_inv_col] acc_idct_colloop1: movq mm0, qword ptr [INP] movq mm1, qword ptr [INP+8] movq mm2, mm0 movq mm3, qword ptr [TABLE] punpcklwd mm0, mm1 movq mm5, mm0 punpckldq mm0, mm0 movq mm4, qword ptr [TABLE+8] punpckhwd mm2, mm1 pmaddwd mm3, mm0 movq mm6, mm2 movq mm1, qword ptr [TABLE+32] punpckldq mm2, mm2 pmaddwd mm4, mm2 punpckhdq mm5, mm5 pmaddwd mm0, qword ptr [TABLE+16] punpckhdq mm6, mm6 movq mm7, qword ptr [TABLE+40] pmaddwd mm1, mm5 paddd mm3, qword ptr [round_inv_col] pmaddwd mm7, mm6 pmaddwd mm2, qword ptr [TABLE+24] paddd mm3, mm4 pmaddwd mm5, qword ptr [TABLE+48] movq mm4, mm3 pmaddwd mm6, qword ptr [TABLE+56] paddd mm1, mm7 paddd mm0, qword ptr [round_inv_col] psubd mm3, mm1 psrad mm3, SHIFT_INV_COL paddd mm1, mm4 paddd mm0, mm2 psrad mm1, SHIFT_INV_COL paddd mm5, mm6 movq mm4, mm0 paddd mm0, mm5 psubd mm4, mm5 add INP, 16 psrad mm4, SHIFT_INV_COL add TABLE, 0 psrad mm0, SHIFT_INV_COL packssdw mm4, mm3 packssdw mm1, mm0 movq mm7, mm4 psrld mm4, 16 movq qword ptr [OUT], mm1 pslld mm7, 16 por mm7, mm4 movq qword ptr [OUT+8], mm7 add edi, 0x01 add OUT, 16 cmp edi, 0x08 jl acc_idct_colloop1 lea OUT, dword ptr [qwTemp] movq mm0, qword ptr [OUT+ROW_STRIDE*0] movq mm1, qword ptr [OUT+ROW_STRIDE*1] movq mm4, mm0 movq mm2, qword ptr [OUT+ROW_STRIDE*2] punpcklwd mm0, mm1 movq mm3, qword ptr [OUT+ROW_STRIDE*3] punpckhwd mm4, mm1 movq mm6, mm2 punpcklwd mm2, mm3 punpckhwd mm6, mm3 movq mm1, mm0 mov INP, dword ptr [block] punpckldq mm0, mm2 movq mm3, mm4 punpckhdq mm1, mm2 movq qword ptr [INP+ROW_STRIDE*0], mm0 punpckldq mm4, mm6 movq mm0, qword ptr [OUT+ROW_STRIDE*4+8] punpckhdq mm3, mm6 movq qword ptr [INP+ROW_STRIDE*2], mm4 movq mm4, mm0 movq qword ptr [INP+ROW_STRIDE*1], mm1 movq mm1, qword ptr [OUT+ROW_STRIDE*5+8] movq qword ptr [INP+ROW_STRIDE*3], mm3 punpcklwd mm0, mm1 movq mm2, qword ptr [OUT+ROW_STRIDE*6+8] punpckhwd mm4, mm1 movq mm3, qword ptr [OUT+ROW_STRIDE*7+8] movq mm6, mm2 punpcklwd mm2, mm3 movq mm1, mm0 punpckhwd mm6, mm3 movq mm3, mm4 punpckldq mm0, mm2 punpckhdq mm1, mm2 movq qword ptr [INP+ROW_STRIDE*4+8], mm0 punpckldq mm4, mm6 movq mm0, qword ptr [OUT+ROW_STRIDE*4] punpckhdq mm3, mm6 movq qword ptr [INP+ROW_STRIDE*6+8], mm4 movq mm4, mm0 movq qword ptr [INP+ROW_STRIDE*5+8], mm1 movq mm1, qword ptr [OUT+ROW_STRIDE*5] movq qword ptr [INP+ROW_STRIDE*7+8], mm3 punpcklwd mm0, mm1 movq mm2, qword ptr [OUT+ROW_STRIDE*6] punpckhwd mm4, mm1 movq mm3, qword ptr [OUT+ROW_STRIDE*7] movq mm6, mm2 punpcklwd mm2, mm3 movq mm1, mm0 punpckhwd mm6, mm3 movq mm3, mm4 punpckldq mm0, mm2 punpckhdq mm1, mm2 movq qword ptr [INP+ROW_STRIDE*0+8], mm0 punpckldq mm4, mm6 movq mm0, qword ptr [OUT+ROW_STRIDE*0+8] punpckhdq mm3, mm6 movq qword ptr [INP+ROW_STRIDE*2+8], mm4 movq mm4, mm0 movq qword ptr [INP+ROW_STRIDE*1+8], mm1 movq mm1, qword ptr [OUT + ROW_STRIDE*1+8] movq qword ptr [INP+ROW_STRIDE*3+8], mm3 punpcklwd mm0, mm1 movq mm2, qword ptr [OUT+ROW_STRIDE*2+8] punpckhwd mm4, mm1 movq mm3, qword ptr [OUT+ROW_STRIDE*3+8] movq mm6, mm2 punpcklwd mm2, mm3 movq mm1, mm0 punpckhwd mm6, mm3 movq mm3, mm4 punpckldq mm0, mm2 punpckhdq mm1, mm2 movq qword ptr [INP+ROW_STRIDE*4], mm0 punpckldq mm4, mm6 movq qword ptr [INP+ROW_STRIDE*5], mm1 punpckhdq mm3, mm6 movq qword ptr [INP+ROW_STRIDE*6], mm4 movq qword ptr [INP+ROW_STRIDE*7], mm3 } }